1. Field of the Invention
The present invention relates in general to design-for-test circuits, and more specifically to a design-for-test circuit that enables industry standard testing including quiescent current testing for low pin count devices including microcontrollers and the like.
2. Description of the Related Art
Various industry standard manufacturing tests are known for testing devices including integrated circuits (ICs) and the like. JTAG or boundary scan testing is relatively common for larger design-for-test (DFT) devices without significant pin count limitations. Scan testing is common for DFT devices which are configured to enable pre-loading of the collective state of the sequential logic of the device. Scan testing can include tests that detect certain faults types, such as stuck-at faults, delay faults, bridging faults, etc. Quiescent current testing, or IDDQ testing, can detect faults or defects that may not be caught by scan testing, such as bridging faults, gate-oxide defects, shorts between any two of the four terminals of a transistor, partial defects that may not affect functionality but that may affect reliability, certain delay faults, certain stuck-open faults, etc.
To conduct scan testing, the IC is configured into a non-user scan test mode and a scan chain sequence is sequentially clocked into an input to load all of the sequential logic. In the scan test mode, every flip-flop (of every register) in the device is serially linked such that the scan chain sequence sequentially propagates to set the state of all flip-flops of the device to set the initial state of the entire device. The device is switched into a quasi-functional mode for at least one clock cycle to exercise the combination logic and the results are sequentially clocked out of an output. The results of each scan test are compared to a predetermined expected value for the scan results. While the results are clocked out, a new scan chain sequence may be clocked in for another test. Any number of scan chain sequences may be used to test as many states as deemed necessary to test the device.
To conduct IDDQ testing, the IC is powered up and placed in a static mode. While in the static state, the quiescent current of the device is measured and compared to a predetermined threshold. A current value below the threshold indicates a passing device. A current value at or above the threshold indicates a failing device. In CMOS logic, P-channel and N-channel devices are coupled together to minimize current flow in either binary logic state. The only current flowing through each device is leakage current if the device is fault-free. The sum total of the leakage current of the fault-free device is determined as the normal quiescent current for that device. Any fault or defect that generates a greater level of current increases the current level over the normal quiescent current level, which is detected when greater than the threshold current level.
It is desired to provide a DFT device on an IC with minimal pin count. Although many complex microprocessors and the like are available with many pins (e.g., hundreds of pins), there are applications requiring microcontrollers with very few pins (e.g., 10 pins or less). The limited number of pins, however, creates problems for testing. The JTAG test methodology requires 4 pins, which is not an option for low pin-count microcontrollers. Scan testing methodology also requires several pins, including a scan input, a scan output, a scan clock input, and a scan enable pin. Also, newer devices are being implemented with low voltage 0.25 micron logic while still requiring a 5 Volt (V) supply voltage. The low voltage logic requires a reduced supply voltage, such as 2.5V or the like, so that the chip must include an internal voltage regulator to convert the higher supply voltage input to the lower voltage level needed for the internal low voltage logic. The voltage regulator consumes a significant level of current and must be turned off or otherwise isolated to ensure reliable IDDQ testing. In one option, a supply voltage pin is provided to the voltage regulator and a separate supply pin is provided to directly source the low voltage devices during testing. In this case, an additional voltage supply pin is required, which is used primarily only for purposes of testing. The inclusion of an additional power supply pin is undesired for low pin-count devices.